This invention relates to a solid-state imaging device for use in a television camera etc. Particularly, it relates to a solid-state imaging device which has a plurality of picture elements disposed in a surface region of a semiconductor body. More specifically, it relates to a solid-state imaging device which has picture elements for reading out from photodiodes thereof photo information stored therein.
As solid-state imaging devices (hereinbelow, termed "image sensors"), the two sorts of a MOS-type device and a CTD-type device have been known. As compared with the latter, the former is higher in the sensing efficiency of light per chip size and is also higher in the sensitivity, but it provides a smaller output signal and is more difficult of signal processing. In such manner, each type has both merits and demerits, so that the known devices have not attained to the performance of a practical level yet.
As an image sensor to solve this problem, there has already been proposed an MCD (MOS-CCD Device) imaging device as shown in FIG. 1, that is, an image sensor which employs a MOS-type structure for a photosensing part and a CTD-type structure for a read-out shift register (Japanese Published Unexamined Utility Model Registration Application No. 54-99579, laid open July 13, 1979).
FIG. 1 shows a photosensor in which a photodiode and an insulated-gate field effect transistor (abbreviated to "MOST") are disposed as a picture element, and a CTD (Charge Transfer Device) is disposed as a read-out register. In the figure, numeral 1 designates a photodiode constructed of a p-n junction utilizing the source junction of a MOST, numeral 2 a vertical switching MOST (abbreviated to "VMOST"), numeral 3 a scanning circuit for sequentially switching the MOSTs 2 by means of clock pulses .phi..sub.v, numeral 4 a vertical signal output line, numeral 5 a horizontal switching MOST (hereinbelow, abbreviated to "HMOST"), numeral 6 a CTD as a read-out shift register, numeral 7 a pre-amplifier connected to the CTD 6, numeral 8 a signal output terminal, and numeral 9 a vertical scanning line. Signal charges which have been read out from the photodiodes through the VMOSTs onto the vertical signal output lines 4 in synchronism with the pulses .phi..sub.v from the scanning circuit 3 are sent through the HMOSTs 5 to the CTD 6 in synchronism with pulses .phi..sub.x and are read out from the pre-amplifier 7 in succession.
As regards the image sensor shown in FIG. 1, excellent characteristics were expected as a device with the merits of the MOS type and the CTD type combined, but in actuality only a very unsatisfactory performance has been obtained for reasons as stated below.
FIG. 2 is a circuit diagram for explaining a problem of the MCD image sensor shown in FIG. 1. In FIG. 2, numeral 10 typically indicates one of the VMOSTs, numeral 11 the corresponding photodiode, numeral 12 one of the HMOSTs, and numeral 13 one transfer and/or storage electrode of the CTD which is the horizontal read-out shift register.
Letting C.sub.p, C.sub.v and C.sub.c denote the respective capacitances of the photodiode 11, the vertical signal output line 14 and the CTD electrode 13 illustrated in FIG. 2, the following relation holds usually: EQU C.sub.v &gt;&gt;C.sub.p,C.sub.c ( 1)
Among the signal charges Q.sub.v delivered to the vertical signal output line, a quantity Q.sub.c of charges which are put into the CTD is: EQU Q.sub.c .perspectiveto.Q.sub.v .multidot.(C.sub.c /C.sub.v) (2)
Herein, however, Q.sub.c &lt;&lt;Q.sub.v holds, so that the signal charges cannot be taken into the CTD sufficiently.
Further, a potential change .DELTA.V.sub.v based on the charges Q.sub.v taken out to the vertical signal output line 14 is very small as compared with a potential change .DELTA.V.sub.p based on a photo signal in the photodiode part, as follows: EQU V.sub.v .perspectiveto.V.sub.p .multidot.(C.sub.p /C.sub.v) (3)
Accordingly, even when the pulse .phi..sub.x has turned "on," the HMOST 12 does not fall into a sufficient conductive state, so that the transfer time of charges is very long and that a satisfactory transfer cannot be executed.
FIG. 3 is an equivalent circuit diagram of a solid-state imaging device which has solved the above problem and which has been proposed by M. Aoki, I. Takemoto, S. Ohba and M. Kubo (Japanese Published Unexamined Utility Model Registration Application No. 55-108756, laid open July 30, 1980). In the figure, numerals 10-14 indicate the same parts as in FIG. 2. In FIG. 3, a transfer MOST (transfer gate) 15, a storage capacitor (storage gate) 16 and a reset MOST (reset gate) 17 are disposed between the vertical signal output line 14 and the HMOST 12.
FIG. 4 is a diagram showing an example of the timings of driving pulses for the image sensor of FIG. 3, and a direction indicated by arrow 30 denotes the "on" state. Hereunder, the operation of the circuit of FIG. 3 will be described with reference to the timings in FIG. 4.
First, before the signal stored in the photodiode 11 is read out, the pulses .phi..sub.t, .phi..sub.s and .phi..sub.R are successively turned "on" as indicated at 22, 23 and 24. Thus, a spurious signal or spurious charges due to dark current etc. having been stored during a horizontal scanning period t.sub.H (29) is/are derived from the reset gate 17, and a potential underneath the storage gate 16 is reset to V.sub.R. Subsequently, the pulses .phi..sub.v, .phi..sub.t, .phi..sub.s and .phi..sub.x are successively turned "on" as indicated at 25, 26, 27 and 28, to transfer the signal to under the storage electrode 13 of the CTD. Here, if V.sub.R is set in advance so that when .phi..sub.t has fallen into the "on" state charges may flow onto the side of the vertical signal output line 14 from a source which is a part underneath the storage gate 16, then the potential of the vertical signal output line 14 can be lowered and the transfer gate 15 falls into a sufficient conductive state. For this reason, when subsequently .phi..sub.s has fallen into the "on" state and the part underneath the storage gate 16 has become the drain side conversely to the above, the charges having flowed in previously and the signal charges can be shifted from the side of the vertical signal output line 14 onto the side of the storage gate 16 in a short time. More specifically, a predetermined quantity of charges are fed to the vertical signal output line 14 from the side of the reset gate 17, and they are caused to flow back onto the side of the storage gate 16 together with the signal charges sent from the side of the diode 11 and are further shifted to the CTD. Thus, it becomes possible to feed most of the signal charges to the CTD in a short time. (The transfer operation stated above is fully performed within a horizontal blanking signal t.sub.B (21 in FIG. 4).)
Here, it is also considered that the reset gate 17 is directly connected with, for example, the vertical signal output line 14. With such connection, however, since C.sub.v &gt;&gt;C.sub.p, C.sub.c and C.sub.s, even a slight change of the potential V.sub.R results in a great change of the quantity of charges, and potential changes underneath the storage gate 16 and the CTD electrode 13 become great, so that a strict control of V.sub.R is needed and that satisfactory characteristics are actually difficult to attain. It is therefore very important to interpose the reset gate 17 between the transfer gate 15 and the HMOST 12.
FIG. 5 is a diagram showing an example which is based on the principle described above. Numerals 1-7 indicate the same parts as in FIG. 1, and numeral 31 designates a transfer gate, numeral 32 a storage gate and numeral 33 a reset gate.
With this system, however, deviations involved in the storage capacitors of respective columns (16 or C.sub.s in FIG. 3, or 32 in FIG. 5) result in the deviations of the signal charges of the respective columns, and the so-called fixed pattern noise in the form of vertical stripes of light shade is noted on a monitor screen obtained by the use of this solid-state imaging device.